Thermal characteristics of integrated circuits have become more important as current densities increase. Even low power silicon technology such as Complimentary Metal Oxide Semiconductor (CMOS) have high enough current densities to warrent circuit and package design that compensates for these increased thermal loads. It is well known in the art that high operating temperatures can deleteriously affect a lifetime of a circuit. For CMOS devices, junction temperatures under 125.degree. C. are low enough to ensure long term operation. The onset of short term failure with CMOS circuits occurs above 125.degree. C.
Individual high lead count packages are utilized for a whole spectrum of integrated circuit dies. Each die will have its own distinct thermal signature. Moreover, an integrated circuit will have several thermal signatures that are a function of the signals received by the device. To be useful for more than one application, a test die must possess the broadest range of power distribution emulation and die sizes. Given the wide variety of packaging materials, component assemblies and interconnect technologies, prior art test dies designed for specific applications have limited utility.
Increasing circuit densities magnify the effect of interconnect design on a device's thermal signature. High lead count packaging interconnect techniques include tape automated bonding (TAB) and flip chip technologies in addition to conventional wire bonding approaches. Prior art test dies do not address the effect of interconnect design on a thermal signature and only allow for wire bond interconnection of the die to the package.